The present invention relates to charge pump system and more particularly, to charge pump oscillators for use in charge pump systems.
Charge pump systems are used by many non-volatile memory devices such as electrically erasable programmable read only memories (EEPROM's) to generate the high internal programming voltages necessary to achieve electron tunneling. The combination of a charge pump circuit and a charge pump oscillator provides the charge pump system.
An example of a charge pump circuit is shown in FIG. 1, labeled prior art. A charge pump circuit includes a plurality of diode ladder stages in which complementary charge pump clock signals are provided to successive stages. The charge pump circuit operates by passing charge along the successive stages of the diode ladder using capacitive coupling of the complementary charge pump clock signals. The complementary charge pump clock signals are provided by the charge pump oscillator.
It is known to drive the charge pump circuit with a free-running delay line type of ring oscillator such as that depicted in FIG. 2, labeled prior art. The frequency of this type of oscillator is heavily dependent upon V.sub.cc because determines the actual delay of the components within the oscillation portion of the charge pump oscillator. The ring oscillator shown in FIG. 2 includes an oscillation portion and a clock driver portion. The oscillation portion provides an input signal to the clock driver portion at terminals "A" and "B".
The ring oscillator functions by connecting an odd number of inverter elements in a circular manner (i.e., in a ring). An input NAND gate provides a means for disabling the oscillator when the enable signal is low. The oscillator outputs are stable (PH1=1, PH2=0) when the enable signal is low. When enabled, the input NAND gate inverts the signal from terminal "A", which signal is then propagated through the inverters back to point "A", which is then fed back to the input NAND gate. The amount of time that it takes the signal to propagate back to point "A" is determined by the inverter delay. This inverter delay is dependent on V.sub.cc because V.sub.cc is the maximum gate-source voltage that can be applied to the transistors within each inverter stage. It is the gate-source voltage which determines the current drive of each inverter stage, which ultimately determines the propagation speed of each inverter stage. The signal which is present at point "A" is then provided to the clock driver portion which provides the PH1 signal. The signal which is present at point "B"0 is provided to the clock drive portion which provides the PH2 signal. The PH1 and PH2 signals are out of phase with each other.
In operation of a charge pump system, the final output voltage (V.sub.out) of the charge pump circuit is dependent upon the starting voltage (V.sub.in) provided to the charge pump circuit, clock voltage (V.sub..phi.) of the charge pump clock signals, number of stages of the diode ladder (N), capacitor size of each stage's capacitor (C), parasitic capacitance to the substrate of the diode junctions (Cs), frequency of the charge: pump clock signals (f), output current load (I.sub.out) and diode threshold voltage (V.sub.D). More specifically, the final output voltage of the charge pump system is set forth by Equation 1 as follows: ##EQU1## Equation 1 can be rearranged in terms of current output to provide Equation 2 as follows: ##EQU2## As can be seen from these equations, variations of the supply voltage affect the operation of the charge pump system in a number of ways. More specifically, a lower value for V.sub.cc causes the charge pump oscillator to generate a lower operating frequency output. Additionally, a lower value for V.sub.cc also translates into lower values for V.sub.in and V.sub..phi.. Thus, the lower value of V.sub.cc causes the charge pump oscillator to generate a lower frequency charge pump clock signal which combines with the lower input voltage levels to make a relatively weak charge pump output voltage. Conversely, a higher value of V.sub.cc causes the charge pump oscillator to generate a higher frequency charge pump clock signal, which combines with the higher input voltage levels to provide a strong charge pump output voltage at higher V.sub.cc levels.